The present invention relates to a current flow reversing circuit, and more particularly, to a current flow reversing circuit for reversing the flow of current to a motor.
A typical example of the circuit for reversing the flow of current flowing into a DC motor is shown in FIG. 1. As shown, an output signal from a control circuit acting as a logical circuit is used for setting up a stop mode, a forward mode and a reverse mode of a motor 12. Relationships among logic levels of control signals applied to the terminals M(+) and M(-) of motor 12 and the input terminals 10A and 10B of a control circuit 11, and the respective modes are tabulated as below.
______________________________________ 10A 10B M(+) M(-) Mode ______________________________________ H L H L Forward H H L H Reverse L H/L High impedance Stop ______________________________________
In the above table, H denotes a high level and L denotes a low level. In a forward mode, the output signal of the control circuit 11 turns on a transistor Q11, and also transistors Q9 and Q5. These transistors Q11, Q9 and Q5 form a current mirror circuit. Upon turning on transistor Q5, a transistor Q1 is appropriately biased to turn on. When transistor Q9 is turned on, transistors Q8 and Q4, which are connected in a Darlington fashion, are appropriately biased and turned on. Then, current flows from the terminal M(+) to the terminal M(-) of motor 12, motor 12 is rotated in the forward direction. For turning the motor in the reverse direction, the output signal of control circuit 11 turns on transistors Q12, Q10 and Q6. Subsequently, transistor Q2 is appropriately biased by transistor Q6. Transistors Q7 and Q3 are also biased by transistor Q10 and turned on. Consequently, the current flows from the terminal M(-) to the terminal M(+), and motor 12 rotates in the reverse direction. For stopping the motor, transistors Q11 and Q12 are both turned off. Accordingly, transistors Q1 to Q4 are not biased and no current is fed to motor 12, thereby to stop motor 12.
In the above circuit, resistors R1 to R6 are provided for preventing an erroneous operation of the circuit due to leak current, and for reducing the off-time of the switching operation of the transistor, viz. reducing the carrier storage effect. The off-time means a time interval between an on-state of the transistor and an off-state.
The terminal currents I.sub.OLf and I.sub.OLr of motor 12 in the forward and the reverse modes are mathematically expressed by ##EQU1## where R.sub.L : Resistance of the motor.
V.sub.CC : Voltage on power line 13. PA1 V.sub.BEQ1 : Voltage across the base-emitter path of transistor Q1. PA1 V.sub.CE(sat)Q5 : Voltage across the collector-emitter path of transistor Q5. PA1 V.sub.BEQ4 : Voltage across the base-emitter path of transistor Q4. PA1 V.sub.CE(sat) : Voltage across of the collector-emitter path of saturated transistor Q8.
In order to increase the currents I.sub.OLf and I.sub.OLr to the amplitude level needed to drive motor 12, a sufficient base current is fed to each transistor Q1 to Q4.
In the above circuit, when motor 12 is steady in the forward or the reverse mode, the current as given by the equation (1) or (2), flows through motor 12. However, if the time period taken for transistor Q1 or Q2 to change its state from the on-state to the off-state, viz. the off-time, is long, a surge current flows through a series circuit comprising transistors Q1 and Q3 or that of transistors Q2 and Q4.
Let us consider a case where a circuit state, in which transistors Q2 and Q3 are in the on-state and transistors Q1 and Q4 are in the off-state (reverse mode), is switched to another state in which transistors Q1 and Q4 are in the on-state and transistors Q2 and Q3 are in the off-state. In this case, if the switching of the transistor to the off-state is delayed, that is, the off-time is long, a surge current flows into the series circuit of transistors Q2 and Q4. This electric current frequently damages transistors Q2 and Q4 or their peripheral circuits.
The switching delay causing the surge current is due to the carrier storage effect of the element when its state is switched from the on-state to the off-state. In the case of the transistors Q1 and Q4, the carrier storage effect changes dependent on the operating current ICQ5 and ICQ9 flowing through transistors Q5 and Q9, which bias transistors Q1 and Q4. The operating current ICQ5 and ICQ9 are given by ##EQU2## where h.sub.FEQ1, h.sub.FEQ4 and h.sub.FEQ8 are DC current amplification factors of transistors Q1, Q4 and Q8, respectively. Since h.sub.FEQ1 =h.sub.FEQ4, EQU I.sub.CQ5 /I.sub.CQ9 =h.sub.FEQ8 ( 5)
As seen from the equation (5), current flowing into transistor Q5 is hFEQ8 times the current flowing into transistor Q9. This implies that the area of transistor Q5 must be much larger than that of transistor Q9, which in turn implies that the storage effect of transistor Q1 is increased accordingly.